Mojo Board FPGA EP.4 - With Mojo&7_Segment
ทดสอบ Single 7 Segment Display – Main Schematic
`timescale 1ns / 1psmodule Decode_7Seg( D, C, B, A, ledt, leda, ledb, ledc, ledd, lede, ledf, ledg);
input D, C, B, A;
output ledt, leda, ledb, ledc, ledd, lede, ledf, ledg;
reg [7:0] seg_data;
reg [3:0] DataIn;
always @* begin
DataIn = { D, C, B, A };
end
always @(DataIn)
case (DataIn)
4'b0000: seg_data = 8'b01111110;
4'b0001: seg_data = 8'b00110000;
4'b0010: seg_data = 8'b01101101;
4'b0011: seg_data = 8'b01111001;
4'b0100: seg_data = 8'b00110011;
4'b0101: seg_data = 8'b01011011;
4'b0110: seg_data = 8'b01011111;
4'b0111: seg_data = 8'b01110000;
4'b1000: seg_data = 8'b01111111;
4'b1001: seg_data = 8'b01111011;
4'b1010: seg_data = 8'b01110111;
4'b1011: seg_data = 8'b00011111;
4'b1100: seg_data = 8'b01001110;
4'b1101: seg_data = 8'b00111101;
4'b1110: seg_data = 8'b01001111;
4'b1111: seg_data = 8'b01000111;
endcase
assign ledt = ~seg_data[7]; // if Active Low(Using ~)
assign leda = ~seg_data[6];
assign ledb = ~seg_data[5];
assign ledc = ~seg_data[4];
assign ledd = ~seg_data[3];
assign lede = ~seg_data[2];
assign ledf = ~seg_data[1];
assign ledg = ~seg_data[0];
endmodule
สร้างวงจรหารความถี่
module Gen_1Hz( input Clk_In, output Clk_Out );
reg rClk_Out;
reg [27:0] Counter;
always@(posedge Clk_In) begin
Counter <= Counter + 1'b1;
if ( Counter == 25_000_000) begin
Counter <= 0;
rClk_Out <= ~rClk_Out;
end
end
assign Clk_Out = rClk_Out;
endmodule
สร้าง Schematic File
สร้าง UCF ไฟล์
NET "Clk_50MHz" LOC = P56 | IOSTANDARD = LVTTL;
NET "Reset_Onboard" LOC = P38 | IOSTANDARD = LVTTL ;
NET "Seg_A" LOC = P41 ;
NET "Seg_B" LOC = P27 ;
NET "Seg_C" LOC = P32 ;
NET "Seg_D" LOC = P40 ;
NET "Seg_E" LOC = P50 ;
NET "Seg_F" LOC = P35 ;
NET "Seg_G" LOC = P29 ;
NET "Seg_T" LOC = P34 ;
// NET "COMM_3" LOC = P51 ;
// NET "COMM_2" LOC = P33 ;
// NET "COMM_1" LOC = P30 ;
NET "COMM_0" LOC = P26 ;
ก็จะได้ 7 segment ตามต้องการ
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